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| Artikel-Nr.: 5667A-9783030981112 Herst.-Nr.: 9783030981112 EAN/GTIN: 9783030981112 |
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| is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Weitere Informationen: | | Author: | Veena S. Chakravarthi; Shivananda R. Koteshwar | Verlag: | Springer International Publishing | Sprache: | eng |
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| Weitere Suchbegriffe: SOC Design, VLSI Physical Design, Clock Tree Synthesis, Standard Cell Library, Tape Out, Unified Power Format (UPF) Flow, Analog Chip Design, VLSI Floor Plan and Placement, Microchips, Fabless Manufacturing, System on Chip |
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